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1995 data sheet description the m pd78094, 78095, 78096, 78098a are members of the m pd78098 subseries of the 78k/0 series of microcontrollers. besides a high-speed and high-performance cpu, each microcontroller has on-chip rom, ram, i/o ports, an iebus tm controller, an 8-bit resolution a/d converter, an 8-bit resolution d/a converter, a timer, serial interface, real-time output port, interrupt control, and various other peripheral hardware. prom versions ( m pd78p098a) will be added to this subseries. these m pd78p098a devices will consist of a one- time prom version and an eprom version, both of which operating in the same power supply voltage range as the mask rom version. various development tools are currently being developed. the details of the functions are described in the following users manuals. be sure to read them before starting design. m pd78098 subseries users manual: ieu-1381 78k/0 series users manual C instructions: ieu-1372 features ? internal high capacity rom and ram 8-bit single-chip microcontrollers item program memory data memory package part (rom) internal high- buffer ram internal number speed ram expansion ram m pd78094 32 kbytes 1024 bytes 32 bytes none 80-pin plastic qfp m pd78095 40 kbytes (14 x 14 mm) m pd78096 48 kbytes m pd78098a 60 kbytes 2048 bytes ? external memory expansion space: 64 kbytes ? instruction execution time can be varied from high-speed (0.5 m s) to ultra-low-speed (122 m s) ? i/o ports: 69 (n-ch open-drain: 4) ? iebus controller ? effective transmission rate: 3.9 kbps/17 kbps/ 26 kbps ? 8-bit resolution a/d converter: 8 channels ? 8-bit resolution d/a converter: 2 channels ? serial interface: 3 channels ? 3-wire/sbi/2-wire mode: 1 channel ? 3-wire mode: 1 channel ? 3-wire/uart mode: 1 channel ? timer: 5 channels ? supply voltage: v dd = 2.7 to 5.5 v applications car audio, cd (compact disk) changer, etc. the information in this document is subject to change without notice. m pd78094, 78095, 78096, 78098a mos integrated circuit document no. u10146ej1v0ds00 (1st edition) date published october 1995 p printed in japan
2 m pd78094, 78095, 78096, 78098a products in mass production products under development y subseries products are compatible with i 2 c bus. 100-pin 100-pin 80-pin 64-pin 64-pin 64-pin 64-pin 42/44pin pd78078 pd78070a pd78054 pd78018f pd78014 pd780001 pd78002 pd78083 m m m m m m m m pd78078y pd78070ay pd78054y pd78018fy pd78014y pd78002y m m m m m m 100-pin 80-pin 64-pin pd780208 pd78044a pd78024 m m m control fip tm drive 100-pin pd78064 m lcd drive m pd78064y 80-pin pd78098 m iebus supported a timer was added to the pd78054 and external interface function was enhanced rom-less versions of the pd78078 uart and d/a converter were added to the pd78014 and i/o was enhanced low-voltage (1.8 v) operation versions of the pd78014 with several rom and ram capacities are available an a/d converter and 16-bit timer were added to the pd78002 an a/d converter was added to the pd78002 basic subseries for control on-chip uart, capable of operating at a low voltage (1.8 v) the i/o and fip c/d of the pd78044a were enhanced, display output total: 53 a 6-bit u/d counter was added to the pd78024, display output total: 34 basic subseries for driving fip, display output total: 26 subseries for driving lcds, on-chip uart the iebus controller was added to the pd78054 m 78k/0 series m m m m m m m m ordering information part number package m pd78094gc- -3b9 80-pin plastic qfp (14 14 mm) m pd78095gc- -3b9 80-pin plastic qfp (14 14 mm) m pd78096gc- -3b9 80-pin plastic qfp (14 14 mm) m pd78098agc- -3b9 80-pin plastic qfp (14 14 mm) remark indicates a rom code suffix. 78k/0 series development the following shows the 78k/0 series products development. subseries names are shown inside frames.
m pd78094, 78095, 78096, 78098a 3 function rom timer 8-bit 8-bit serial interface i/o v dd min. external part number capacity 8-bit 16-bit watch wdt a/d d/a value expansion control m pd78078 32k-60k 4ch 1ch 1ch 1ch 8ch 2ch 3ch (uart: 1ch) 88 1.8 v available m pd78070a C 61 2.7 v m pd78054 16k-60k 2ch 69 2.0 v m pd78018f 8k-48k C 2ch 53 1.8 v m pd78014 8k-32k 2.7 v m pd780001 8k C C 1ch 39 C m pd78002 8k-16k 1ch C 53 available m pd78083 C 8ch 1ch (uart: 1ch) 33 1.8 v C fip drive m pd780208 32k-40k 2ch 1ch 1ch 1ch 8ch C 2ch 74 2.7 v C m pd78044a 16k-40k 68 m pd78024 24k-32k 54 lcd drive m pd78064 16k-32k 2ch 1ch 1ch 1ch 8ch C 2ch (uart: 1ch) 57 2.0 v C iebus m pd78098 32k-60k 2ch 1ch 1ch 1ch 8ch 2ch 3ch (uart: 1ch) 69 2.7 v available supported the following table shows the differences among subseries functions.
4 m pd78094, 78095, 78096, 78098a overview of function part number m pd78094 m pd78095 m pd78096 m pd78098a item internal rom 32 kbytes 40 kbytes 48 kbytes 60 kbytes memory internal high-speed ram 1024 bytes buffer ram 32 bytes internal expansion ram none 2048 bytes memory space 64 kbytes general registers 8 bits 32 registers (8 bits 8 registers 4 banks) instruction cycle on-chip instruction execution time cycle variable function when main system 0.5 m s/1.0 m s/2.0 m s/4.0 m s/8.0 m s/16.0 m s (at main system clock of 6.0 mhz) clock selected when subsystem 122 m s (at subsystem clock of 32.768 khz) clock selected instruction set ? 16-bit operation ? multiply/divide (8 bits 8 bits, 16 bits ? 8 bits) ? bit manipulate (set, reset, test, boolean operation) ? bcd adjust, etc. i/o ports total : 69 ? cmos input : 2 ? cmos i/o : 63 ? n-ch open-drain i/o : 4 iebus controller effective transmission rate : 3.9 kbps/17 kbps/26 kbps a/d converter ? 8-bit resolution 8 channels d/a converter ? 8-bit resolution 2 channels serial interface ? 3-wire/sbi/2-wire mode selectable : 1 channel ? 3-wire mode (on-chip max. 32 bytes automatic data transmit/receive function): 1 channel ? 3-wire/uart mode selectable : 1 channel timer ? 16-bit timer/event counter : 1 channel ? 8-bit timer/event counter : 2 channels ? watch timer : 1 channel ? watchdog timer : 1 channel timer output 3 (14-bit pwm output 1) clock output 15.6 khz, 31.3 khz, 62.5 khz, 125 khz, 250 khz, 500 khz, 1.0 mhz, 2.0 mhz, 4.0 mhz (at main system clock of 6.0 mhz) 32.768 khz (at subsystem clock of 32.768 khz) buzzer output 977 hz, 1.95 khz, 3.9 khz, 7.8 khz (at main system clock of 6.0 mhz) vectored maskable interrupts internal: 14, external: 7 interrupts non-maskable interrupt internal: 1 software interrupt internal: 1 test input internal: 2, external: 1 supply voltage v dd = 2.7 to 5.5 v package 80-pin plastic qfp (14 x 14 mm)
m pd78094, 78095, 78096, 78098a 5 contents 1. pin configuration (top view) ............................................................................................ 7 2. block diagram ........................................................................................................................ 9 3. pin functions ......................................................................................................................... 10 3.1 port pins ............................................................................................................................... ................. 10 3.2 non-port pins ............................................................................................................................... ......... 12 3.3 pin i/o circuits and recommended connection of unused pins ...................................................... 14 4. memory space ........................................................................................................................ 18 5. peripheral hardware functions ................................................................................. 19 5.1 ports ............................................................................................................................... ....................... 19 5.2 clock generator ............................................................................................................................... ..... 20 5.3 timer/event counter ............................................................................................................................. 21 5.4 clock output control circuit ................................................................................................................. 23 5.5 buzzer output control circuit ............................................................................................................... 24 5.6 a/d converter ............................................................................................................................... ......... 24 5.7 d/a converter ............................................................................................................................... ......... 25 5.8 serial interfaces ............................................................................................................................... ..... 25 5.9 real-time output port .......................................................................................................................... 27 5.10 iebus controller ............................................................................................................................... .... 28 6. interrupt functions and test functions ............................................................... 29 6.1 interrupt functions ............................................................................................................................... .29 6.2 test functions ............................................................................................................................... ........ 32 7. external device expansion functions ...................................................................... 33 8. standby function ................................................................................................................ 33 9. reset function ..................................................................................................................... 33 10. instruction set .................................................................................................................... 34 11. electrical specifications ............................................................................................... 37 12. characteristic curves (reference values) .......................................................... 64 13. package drawing ................................................................................................................ 66
6 m pd78094, 78095, 78096, 78098a 14. recommended soldering conditions ......................................................................... 67 appendix a. development tools ........................................................................................... 68 appendix b. related documents ........................................................................................... 69
m pd78094, 78095, 78096, 78098a 7 p15/ani5 p16/ani6 p17/ani7 av ss p130/ano0 p131/ano1 av ref1 p70/si2/rxd p71/so2/txd p72/sck2/asck p20/si1 p21/so1 p22/sck1 p23/stb p24/busy p25/si0/sb0 p26/so0/sb1 p27/sck0 p40/ad0 p41/ad1 p42/ad2 p43/ad3 p44/ad4 p45/ad5 p46/ad6 p47/ad7 p50/a8 p51/a9 p52/a10 p53/a11 p54/a12 p55/a13 v ss p56/a14 p57/a15 p60 p61 p62 p63 p64/rd reset p127/rtp7 p126/rtp6 p125/rtp5/rx p124/rtp4/tx p123/rtp3 p122/rtp2 p121/rtp1 p120/rtp0 p37 p36/buz p35/pcl p34/ti2 p33/ti1 p32/to2 p31/to1 p30/to0 p67/astb p66/wait p65/wr p14/ani4 p13/ani3 p12/ani2 p11/ani1 p10/ani0 av ref0 av dd xt1/p07 xt2 ic x1 x2 v dd p06/intp6 p05/intp5 p04/intp4 p03/intp3 p02/intp2 p01/intp1/ti01 p00/intp0/ti00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 1. pin configuration (top view) ? 80-pin plastic qfp (14 14 mm) m pd78094gc- -3b9 m pd78095gc- -3b9 m pd78096gc- -3b9 m pd78098agc- -3b9 cautions 1. connect ic (internally connected) pin directly to v ss . 2. av dd pin should be connected to v dd . 3. av ss pin should be connected to v ss .
8 m pd78094, 78095, 78096, 78098a p00Cp07 : port0 rx : receive data (iebus controller) p10Cp17 : port1 tx : transmit data (iebus controller) p20Cp27 : port2 pcl : programmable clock p30Cp37 : port3 buz : buzzer clock p40Cp47 : port4 stb : strobe p50Cp57 : port5 busy : busy p60Cp67 : port6 ad0Cad7 : address/data bus p70Cp72 : port7 a8Ca15 : address bus p120Cp127 : port12 rd : read strobe p130, p131 : port13 wr : write strobe rtp0Crtp7 : realtime output port wait : wait intp0Cintp6 : interrupt from peripherals astb : address strobe ti00, ti01 : timer input x1, x2 : crystal (main system clock) ti1, ti2 : timer input xt1, xt2 : crystal (subsystem clock) to0Cto2 : timer output reset : reset sb0, sb1 : serial bus ani0Cani7 : analog input si0Csi2 : serial input ano0, ano1 : analog output so0Cso2 : serial output av dd : analog power supply sck0Csck2 : serial clock av ss : analog ground rxd : receive data (uart) av ref0, 1 : analog reference voltage txd : transmit data (uart) v dd : power supply asck : asynchronous serial clock v ss : ground ic : internally connected
m pd78094, 78095, 78096, 78098a 9 port 0 port 1 port 2 port 3 port 4 port 5 port 6 port 7 port 12 port 13 p01-p06 p10-p17 p20-p27 p30-p37 p40-p47 p50-p57 p60-p67 p70-p72 p120-p127 p130, p131 p00 p07 to0/p30 ti00/intp0/p00 ti01/intp1/p01 to1/p31 ti1/p33 to2/p32 ti2/p34 16-bit timer/ event counter 8-bit timer/ event counter 1 8-bit timer/ event counter 2 watchdog timer watch timer si0/sb0/p25 so0/sb1/p26 sck0/p27 serial interface 0 si1/p20 so1/p21 sck1/p22 stb/p23 busy/p24 serial interface 1 si2/rxd/p70 so2/txd/p71 sck2/asck/p72 serial interface 2 ani0/p10- ani7/p17 av dd av ss av ref0 ano0/p130, ano1/p131 av ss av ref1 d/a converter a/d converter interrupt control intp0/p00- intp6/p06 realtime output port rtp0/p120- rtp7/p127 iebus controller tx/p124/rtp4 rx/p125/rtp5 buzzer output buz/p36 clock output control pcl/p35 78k/0 cpu core rom ram external access system control v dd v ss ic ad0/p40- ad7/p47 a8/p50- a15/p57 rd/p64 wr/p65 wait/p66 astb/p67 reset x1 x2 xt1/p07 xt2 2. block diagram
m pd78094, 78095, 78096, 78098a 10 3. pin functions 3.1 port pins (1/2) notes 1. when using the p07/xt1 pins as an input port, set 1 to bit 6 of the processor clock control register (frc). do not use the on-chip feedback resistor of the subsystem clock oscillator. 2. when using the p10/ani0 to p17/ani7 pins as the a/d converter analog input, the pull-up resistor is automatically disconnected. pin name i/o function after alternate reset function pin p00 input port 0 input only input intp0/ti00 p01 input/ 8-bit i/o port input/output can be specified bit-wise. input intp1/ti01 p02 output when used as an input port, pull-up resistor intp2 p03 can be connected by software. intp3 p04 intp4 p05 intp5 p06 intp6 p07 note 1 input input only input xt1 p10-p17 input/ port 1 input ani0-ani7 output 8-bit input/output port. input/output can be specified bit-wise. when used as an input port, pull-up resistor can be connected by software. note 2 p20 input/ port 2 input si1 p21 output 8-bit input/output port. so1 p22 input/output can be specified bit-wise. sck1 p23 when used as an input port, pull-up resistor can be connected by software. stb p24 busy p25 si0/sb0 p26 so0/sb1 p27 sck0 p30 input/ port 3 input to0 p31 output 8-bit input/output port. to1 p32 input/output can be specified bit-wise. to2 p33 when used as an input port, pull-up resistor can be connected by software. ti1 p34 ti2 p35 pcl p36 buz p37 p40-p47 input/ port 4 input ad0-ad7 output 8-bit input/output port. input/output can be specified in 8-bit units. when used as an input port, pull-up resistor can be connected by software.
m pd78094, 78095, 78096, 78098a 11 3.1 port pins (2/2) pin name i/o function after alternate reset function pin p50-p57 input/ port 5 input a8-a15 output 8-bit input/output port. leds can be driven directly. input/output can be specified bit-wise. when used as an input port, pull-up resistor can be connected by software. p60 input/ port 6 n-ch open-drain input/output input p61 output 8-bit input/output port. port. on-chip pull-up resistor p62 input/output can be can be specified by mask option. p63 specified bit-wise. led can be driven directly. p64 when used as an input port, input rd p65 pull-up resistor can be wr p66 connected by software. wait p67 astb p70 input/ port 7 input si2/rxd p71 output 3-bit input/output port. so2/txd p72 input/output can be specified bit-wise. sck2/asck when used as an input port, pull-up resistor can be connected by software. p120-p123 input/ port 12 input rtp0-rtp3 p124 output 8-bit input/output port. rtp4/tx p125 input/output can be specified bit-wise. rtp5/rx p126, p127 when used as an input port, pull-up resistor can be connected by software. rtp6, rtp7 p130, p131 input/ port 13 input ano0, ano1 output 2-bit input/output port. input/output can be specified bit-wise. when used as an input port, pull-up resistor can be connected by software.
m pd78094, 78095, 78096, 78098a 12 pin name i/o function after alternate reset function pin intp0 input external interrupt input by which the active edge (rising edge, falling edge, or input p00/ti00 intp1 both rising and falling edges) can be specified. p01/ti01 intp2 p02 intp3 p03 intp4 p04 intp5 p05 intp6 p06 si0 input serial interface serial data input. input p25/sb0 si1 p20 si2 p70/rxd so0 output serial interface serial data output. input p26/sb1 so1 p21 so2 p71/txd sb0 input/ serial interface serial data input/output. input p25/si0 sb1 output p26/so0 sck0 input/ serial interface serial clock input/output. input p27 sck1 output p22 sck2 p72/asck stb output serial interface automatic transmit/receive strobe output. input p23 busy input serial interface automatic transmit/receive busy input. input p24 rxd input asynchronous serial interface serial data input. input p70/si2 txd output asynchronous serial interface serial data output. input p71/so2 asck input asynchronous serial interface serial clock input. input p72/sck2 ti00 input external count clock input to 16-bit timer (tm0). input p00/intp0 ti01 capture trigger signal input to capture register (cr00). p01/intp1 ti1 external count clock input to 8-bit timer (tm1). p33 ti2 external count clock input to 8-bit timer (tm2). p34 to0 output 16-bit timer output (also used for 14-bit pwm output). input p30 to1 8-bit timer output. p31 to2 p32 pcl output clock output (for main system clock, subsystem clock trimming). input p35 buz output buzzer output. input p36 rtp0-rtp3 output real-time output port by which data is output in synchronization with a trigger. input p120-p123 rtp4 p124/tx rtp5 p125/rx rtp6, rtp7 p126, p127 tx output iebus controller data output input p124/rtp4 rx input iebus controller data input input p125/rtp5 3.2 non-port pins (1/2)
m pd78094, 78095, 78096, 78098a 13 3.2 non-port pins (2/2) pin name i/o function after alternate reset function pin ad0-ad7 input/ low-order address/data bus at external memory expansion. input p40-p47 output a8-a15 output high-order address bus at external memory expansion. input p50-p57 rd output external memory read operation strobe signal output. input p64 wr external memory write operation strobe signal output. p65 wait input wait insertion at external memory access. input p66 astb output strobe output which latches the address data output for ports 4 or 5 to access input p67 external memory. an10-an17 input a/d converter analog input. input p10-p17 ano0, ano1 output d/a converter analog output. input p130, p131 av ref0 input a/d converter reference voltage input. av ref1 input d/a converter reference voltage input. av dd a/d converter analog power supply. connect to v dd . av ss a/d converter ground potential. connect to v ss . reset input system reset input. x1 input main system clock oscillation crystal connection. x2 xt1 input subsystem clock oscillation crystal connection. input p07 xt2 v dd positive power supply. v ss ground potential. ic internal connection. connected directly to v ss .
m pd78094, 78095, 78096, 78098a 14 3.3 pin i/o circuits and recommended connection of unused pins the input/output circuit type of each pin and recommended connection of unused pins are shown in table 3-1. for the input/output circuit configuration of each type, see figure 3-1. table 3-1. types of pin input/output circuits (1/2) pin name input/output i/o recommended connection for unused pins circuit type p00/intp0/ti00 2 input connect to v ss . p01/intp1/ti01 8-a input/output independently connect to v ss via a resistor. p02/intp2 p03/intp3 p04/intp4 p05/intp5 p06/intp6 p07/xt1 16 input connect to v dd or v ss . p10/ani0-p17/ani7 11 input/output independently connect to v dd or v ss via a resistor. p20/si1 8-a p21/so1 5-a p22/sck1 8-a p23/stb 5-a p24/busy 8-a p25/si0/sb0 10-a p26/so0/sb1 p27/sck0 p30/to0 5-a p31/to1 p32/to2 p33/ti1 8-a p34/ti2 p35/pcl 5-a p36/buz p37 p40/ad0-p47/ad7 5-e independently connect to v dd via a resistor. p50/a8-p57/a15 5-a independently connect to v dd or v ss via a resistor. p60-p63 13-b independently connect to v dd via a resistor. p64/rd 5-a independently connect to v dd or v ss via a resistor. p65/wr p66/wait p67/astb
m pd78094, 78095, 78096, 78098a 15 table 3-1. types of pin input/output circuits (2/2) pin name input/output i/o recommended connection for unused pins circuit type p70/si2/rxd 8-a input/output independently connect to v dd or v ss via a resistor. p71/so2/txd 5-a p72/sck2/asck 8-a p120/rtp0-p123/rtp3 5-a p124/rtp4/tx p125/rtp5/rx p126/rtp6, p127/rtp7 p130/ano0, 12-a independently connect to v ss via a resistor. p131/ano1 reset 2 input xt2 16 leave open. av ref0 connect to v ss . av ref1 connect to v dd . av dd av ss connect to v ss . ic connect directly to v ss .
m pd78094, 78095, 78096, 78098a 16 type 2 in type 8-a pullup enable data output disable v dd p-ch n-ch p-ch in/out v dd type 10-a type 11 pullup enable data output disable v dd p-ch n-ch p-ch in/out v dd type 5-a input enable type 5-e pullup enable data output disable v dd p-ch n-ch p-ch in/out v dd schmitt-triggered input with hysteresis characteristics pullup enable data open drain output disable n-ch p-ch v dd v dd p-ch in/out pullup enable data output disable input enable n-ch v dd p-ch in/out v dd p-ch p-ch n-ch v ref (threshold voltage) comparator + figure 3-1. pin input/output circuits (1/2)
m pd78094, 78095, 78096, 78098a 17 figure 3-2. pin input/output circuits (2/2) type 12-a type 16 pullup enable data output disable v dd p-ch n-ch p-ch in/out v dd n-ch input enable type 13-b data output disable n-ch in/out v dd v dd rd mask option middle-high voltage input buffer p-ch analog output voltage xt1 xt2 p-ch feedback cut-off p-ch
m pd78094, 78095, 78096, 78098a 18 4. memory space the memory map of the m pd78094, 78095, 78096, and 78098a is shown in figure 4-1. figure 4-1. memory map notes 1. only m pd78098a. 2. when using the external device expansion function with the m pd78098a, set the internal rom capacity to below 56 kbytes by using a memory size switching register. 3. internal rom capacity is different among products. target internal rom last address target internal rom last address part number nnnnh part number nnnnh m pd78094 7ffffh m pd78096 bfffh m pd78095 9ffffh m pd78098a efffh remark shaded areas indicate internal memory. ff00h feffh fee0h fedfh ffffh fb00h faffh fae0h fadfh fac0h fabfh f900h f8ffh f8e0h f8dfh f800h f7ffh f000h efffh nnnnh 0000h 0000h 0040h 003fh 0080h 007fh 0800h 07ffh 1000h 0fffh nnnnh f000h f7ffh data memory space use prohibited use prohibited external memory use prohibited use prohibited program area callf entry area program area callt table area vector table area program memory space nnnnh+1 internal expansion ram 2048 x 8 bits special function registers (sfr) 256 8 bits general registers 32 8 bits internal high-speed ram 1024 8 bits buffer ram 32 8 bits iebus registers 32 8 bits internal rom note 3 notes 1, 2
m pd78094, 78095, 78096, 78098a 19 port name pin name function port 0 p00, p07 input only. p01-p06 input/output port. input/output can be specified bit-wise. when used as an input port, on-chip pull-up resistor can be connected by software. port 1 p10-p17 input/output port. input/output can be specified bit-wise. when used as an input port, on-chip pull-up resistor can be connected by software. port 2 p20-p27 input/output port. input/output can be specified bit-wise. when used as an input port, on-chip pull-up resistor can be connected by software. port 3 p30-p37 input/output port. input/output can be specified bit-wise. when used as an input port, on-chip pull-up resistor can be connected by software. port 4 p40-p47 input/output port. input/output can be specified in 8-bit units. when used as an input port, on-chip pull-up resistor can be connected by software. the test input flag (krif) is set to 1 by falling edge detection. port 5 p50-p57 input/output port. input/output can be specified bit-wise. when used as an input port, on-chip pull-up resistor can be connected by software. leds can be driven directly. port 6 p60-p63 n-ch open-drain input/output port. input/output can be specified bit-wise. on-chip pull-up resistor can be connected by mask option. leds can be driven directly. p64-p67 input/output port. input/output can be specified bit-wise. when used as an input port, on-chip pull-up resistor can be connected by software. port 7 p70-p72 input/output port. input/output can be specified bit-wise. when used as an input port, on-chip pull-up resistor can be connected by software. port 12 p120-p127 input/output port. input/output can be specified bit-wise. when used as an input port, on-chip pull-up resistor can be connected by software. port 13 p130, p131 input/output port. input/output can be specified bit-wise. when used as an input port, on-chip pull-up resistor can be connected by software. 5. peripheral hardware functions 5.1 ports input/output ports are classified into three types. ? cmos input (p00, p07) : 2 ? cmos input/output (p01-p06, ports 1-5, p64-p67, port 7, port 12, port 13) : 63 ? n-ch open-drain input/output (p60-p63) : 4 total :69 table 5-1. functions of ports
m pd78094, 78095, 78096, 78098a 20 5.2 clock generator there are two kinds of clock generators: main system and subsystem clock generators. it is possible to change the instruction execution time. ? 0.5 m s/1.0 m s/2.0 m s/4.0 m s/8.0 m s/16.0 m s (at main system clock frequency of f xx = 6.0 mhz) ? 122 m s (at subsystem clock frequency of f xt = 32.768 khz) figure 5-1. clock generator block diagram selector 1/2 selector 1/3 selector 2/3 selector 1/2 1/2 prescaler cpu clock (f cpu ) prescaler selector xt1/p07 xt2 x1 x2 subsystem clock oscillator main system clock oscillator stop f x clock to iebus controller f xx f xx 2 f xx 2 2 f xx 2 3 f xx 2 4 f xt 2 standby control circuit wait control circuit to intp0 sampling clock clock to peripheral hardware watch timer, clock output function f xt
m pd78094, 78095, 78096, 78098a 21 5.3 timer/event counter there are the following five timer/event counter channels: ? 16-bit timer/event counter : 1 channel ? 8-bit timer/event counter : 2 channels ? watch timer : 1 channel ? watchdog timer : 1 channel table 5-2. types and functions of timer/event counters 16-bit timer/event 8-bit timer/event watch timer watchdog timer counter counter type interval timer 1 channel 2 channels 1 channel 1 channel external event counter 1 channel 2 channels function timer output 1 output 2 outputs pwm output 1 output pulse width measurement 2 inputs square wave output 1 output 2 outputs one-shot pulse output 1 output interrupt request 2 2 1 1 test input 1 figure 5-2. 16-bit timer/event counter block diagram match match clear selector 16-bit capture/ compare register (cr00) internal bus output control circuit intp1 inttm00 to0/p30 inttm01 intp0 ti01/p01/ intp1 watch timer output 2f xx f xx f xx /2 f xx /2 ti00/p00/ intp0 selector edge detector selector internal bus 16-bit capture/ compare register (cr01) pwm pulse output control circuit 16-bit timer register (tm0) 2
m pd78094, 78095, 78096, 78098a 22 figure 5-3. 8-bit timer/event counter block diagram figure 5-4. watch timer block diagram f w 4 2 f w 5 2 f w 6 2 f w 7 2 f w 8 2 f w 9 2 f w 13 2 f w 2 f xt selector 5-bit counter selector prescaler selector intwt inttm3 selector f w 14 to 16-bit timer/ event counter f xx/ 7 2 clear clear 11 f /2 xx - f /2 xx 9 ti2/p34 ti1/p33 inttm2 to2/p32 to1/p31 match match inttm1 f /2 xx 11 f/2 xx - f /2 xx 9 f /2 xx internal bus selector selector selector 8-bit timer register 1 (tm1) 8-bit compare register (cr20) 8-bit compare register (cr10) output control circuit 8-bit timer register 2 (tm2) output control circuit internal bus selector selector
m pd78094, 78095, 78096, 78098a 23 figure 5-5. watchdog timer block diagram 5.4 clock output control circuit this circuit can output clocks of the following frequencies: ? 15.6 khz/31.3 khz/62.5 khz/125 khz/250 khz/500 khz/1.0 mhz/2.0 mhz/4.0 mhz (at main system clock frequency of f xx = 6.0 mhz) ? 32.768 khz (at subsystem clock frequency of f xt = 32.768 khz) figure 5-6. clock output control circuit block diagram f xx f xx 5 f xx 6 f xx 7 2 f xx 8 2 f xx 9 2 f xx 11 2 intwdt maskable interrupt request reset intwdt non-maskable interrupt request prescaler selector control circuit 4 22 2 8-bit counter f xx 3 2 pcl/p35 f xx /2 2 f xx /2 3 f xx /2 4 f xx /2 5 f xx /2 6 f xx /2 7 f xt synchronization circuit f xx /2 f xx selector output control circuit
m pd78094, 78095, 78096, 78098a 24 5.5 buzzer output control circuit this circuit can output clocks of the following frequencies that can be used for driving buzzers: ? 977 hz/1.95 khz/3.9 khz/7.8 khz (at main system clock frequency of f xx = 6.0 mhz) figure 5-7. buzzer output control circuit block diagram 5.6 a/d converter the a/d converter consists of eight 8-bit resolution channels. a/d conversion can be started by the following two methods: ? hardware starting ? software starting figure 5-8. a/d converter block diagram selector output control circuit buz/p36 f xx /2 9 f xx /2 10 f xx /2 11 intp3/p03 tap selector ani0/p10 ani2/p12 ani3/p13 ani4/p14 ani5/p15 ani6/p16 ani7/p17 ani1/p11 av dd av ref0 av ss intad intp3 series resistor string selector sample & hold circuit voltage comparator successive approximation register (sar) edge detector control circuit a/d conversion result register (adcr) internal bus connection control
m pd78094, 78095, 78096, 78098a 25 5.7 d/a converter the d/a converter consists of two 8-bit resolution channels. the conversion method is the r-2r resistor ladder method. figure 5-9. d/a converter block diagram n = 0, 1 m = 4, 5 x = 1, 2 function serial interface channel 0 serial interface channel 1 serial interface channel 2 3-wire serial i/o mode (msb/lsb first (msb/lsb first (msb/lsb first switching possible) switching possible) switching possible) 3-wire serial i/o mode with (msb/lsb first automatic data transmit/receive switching possible) function 2-wire serial i/o mode (msb first) sbi (serial bus interface) mode (msb first) asynchronous serial interface (on-chip dedicated baud (uart) mode rate generator) 5.8 serial interfaces there are the following three on-chip serial interface channels synchronous with the clock: ? serial interface channel 0 ? serial interface channel 1 ? serial interface channel 2 table 5-3. types and functions of serial interfaces internal bus selector d/a conversion value set register n (dacsn) av ref1 av ss d/a converter mode register damm inttm x dacsn write anon
m pd78094, 78095, 78096, 78098a 26 internal bus buffer ram automatic data transmit/ receive address pointer (adtp) serial i/o shift register 1 (sio1) automatic data transmit/receive interval specification register (adti) match 5-bit counter selector handshake control circuit serial clock counter si1/p20 so1/p21 stb/p23 busy/p24 sck1/p22 intcsi1 f xx /2? xx /2 8 to2 interrupt request signal generator serial clock control circuit selector busy/acknowledge output circuit internal bus selector interrupt request signal generator to2 intcsi0 f xx /2? xx /2 8 si0/sb0/p25 so0/sb1/p26 sck0/p27 serial clock control circuit bus release/command/ acknowledge detector serial clock counter serial i/o shift register 0 (sio0) selector output latch figure 5-10. serial interface channel 0 block diagram figure 5-11. serial interface channel 1 block diagram
m pd78094, 78095, 78096, 78098a 27 receive buffer register (rxb/sio2) internal bus direction control circuit direction control circuit transmit shift register (txs/sio2) receive shift register (rxs) receive control circuit transmit control circuit sck output control circuit baud rate generator intser intst intsr/intcsi2 f xx ? xx /2 10 asck/sck2/p72 t x d/so2/p71 r x d/si2/p70 figure 5-12. serial interface channel 2 block diagram p127 p120 output trigger control circuit intp2 inttm1 inttm2 output latch real-time output buffer register lower 4 bits (rtbl) real-time output buffer register higher 4 bits (rtbh) internal bus real-time output port mode register (rtpm) 5.9 real-time output port data set previously in the real-time output buffer is transferred to the output latch by hardware concurrently with timer interrupt or external interrupt generation in order to output to off-chip. this is a real-time output function. pins used to output to off-chip are called real-time output ports. by using a real-time output port, a signal which has no jitter can be output. this is most applicable to control of stepping motors, etc. figure 5-13. real-time output port block diagram
m pd78094, 78095, 78096, 78098a 28 5.10 iebus controller iebus (inter equipment bus tm ) is a small-scale digital data transmission system for transmitting data between units. when configuring the iebus with the m pd78098 subseries, the iebus driver/receiver need to be connected externally as they are not incorporated. using the iebus controller incorporated in the m pd78098 subseries, positive logic/negative logic can be selected by software for the externally connected iebus driver/receiver.
m pd78094, 78095, 78096, 78098a 29 interrupt default note1 interrupt factor internal/ vector basic note2 type priority name trigger external table structure address type non- intwdt overflow of watchdog timer (when the watchdog timer internal 0004h (a) maskable mode 1 is selected) maskable 0 intwdt overflow of watchdog timer (when the interval timer (b) mode is selected) 1 intp0 pin input edge detection external 0006h (c) 2 intp1 0008h (d) 3 intp2 000ah 4 intp3 000ch 5 intp4 000eh 6 intp5 0010h 7 intp6 0012h 8 intcsi0 completion of serial interface channel 0 transfer internal 0014h (b) 9 intcsi1 completion of serial interface channel 1 transfer 0016h 10 intser occurrence of serial interface channel 2 uart reception 0018h error 11 intsr completion of serial interface channel 2 uart reception 001ah intcsi2 completion of serial interface channel 2 3-wire transfer 12 intst completion of serial interface channel 2 uart 001ch transmission 13 inttm3 reference interval signal from watch timer 001eh 14 inttm00 generation of matching signal of 16-bit timer register 0020h and capture/compare register (cr00) 15 inttm01 generation of matching signal of 16-bit timer register 0022h and capture/compare register (cr01) 16 inttm1 generation of matching signal of 8-bit timer/event 0024h counter 1 17 inttm2 generation of matching signal of 8-bit timer/event 0026h counter 2 18 intad completion of a/d conversion 0028h 19 intie writing data from the iebus controller to the return code 002ah register (rcr) (including the same value) or detecting an iebus interface runaway. software brk execution of brk instruction internal 003eh (e) 6. interrupt functions and test functions 6.1 interrupt functions a total of 23 interrupt functions are provided, divided into the following three types. ? non-maskable interrupt : 1 ? maskable interrupts : 21 ? software interrupt : 1 table 6-1. list of interrupt factors notes 1. default priority is the priority order when several maskable interrupts are generated at the same time. 0 is the highest order and 19 is the lowest order. 2. basic structure types (a) to (e) correspond to (a) to (e) in figure 6-1.
m pd78094, 78095, 78096, 78098a 30 figure 6-1. interrupt function basic configuration (1/2) (a) internal non-maskable interrupt interrupt request standby release signal internal bus vector table address generator priority control circuit (b) internal maskable interrupt mk ie pr isp if interrupt request internal bus priority control circuit vector table address generator standby release signal (c) external maskable interrupt (intp0) sampling clock select register (scs) if ie pr isp external interrupt mode register (intm0) sampling clock edge detector interrupt request internal bus mk priority control circuit vector table address generator standby release signal
m pd78094, 78095, 78096, 78098a 31 figure 6-1. interrupt function basic configuration (2/2) (d) external maskable interrupt (except intp0) if internal bus interrupt request edge detector vector table address generator standby release signal external interrupt mode register (intm0, intm1) mk ie pr isp priority control circuit (e) software interrupt internal bus interrupt request vector table address generator priority control circuit if : interrupt request flag ie : interrupt enable flag isp : in-service priority flag mk : interrupt mask flag pr : priority specification flag
m pd78094, 78095, 78096, 78098a 32 6.2 test functions table 6-2 shows the two test functions available. table 6-2. test input factors test input factor internal/ name trigger external intwt overflow of watch timer internal intpt4 detection of falling edge of port 4 external figure 6-2. basic configuration of test function mk if internal bus standby release signal test input signal if : test input flag mk : test mask flag
m pd78094, 78095, 78096, 78098a 33 main system clock operation subsystem clock operation note interrupt request stop instruction stop mode (oscillation of the main system clock is stopped.) interrupt request interrupt request halt instruction halt mode (supply of clock to cpu is stopped although clock is generated.) halt instruction halt mode note (supply of clock to cpu is stopped although clock is generated.) css = 1 css = 0 7. external device expansion functions the external device expansion functions connect external devices to areas other than the internal rom, ram, and sfr. external devices connection uses ports 4 to 6. 8. standby function the standby function is designed to reduce current consumption. it has the following two modes: ? halt mode : in this mode, the cpu operation clock is stopped. the average current consumption can be reduced by intermittent operation by combining this mode with the normal operation mode. ? stop mode : in this mode, oscillation of the main system clock is stopped. all the operations performed on the main system clock are suspended, and only the subsystem clock is used for extremely small power consumption. figure 8-1. standby function note current consumption is reduced by shutting off the main system clock. if the cpu is operating on the subsystem clock, shut off the main system clock by setting mcc. you cannot use a stop instruction. caution when switching on the main system clock again after the subsystem clock has been used with the main system clock stopped, be sure to provide enough time for the generation to be stable with the program first. 9. reset function there are the following two reset methods. ? external reset input by reset pin ? internal reset by watchdog timer runaway time detection
m pd78094, 78095, 78096, 78098a 34 10. instruction set (1) 8-bit instructions mov, xch, add, addc, sub, subc, and, or, xor, cmp, mulu, divuw, inc, dec, ror, rol, rorc, rolc, ror4, rol4, push, pop, dbnz 2nd operand #byte a r note sfr saddr !addr16 psw [de] [hl] [hl + byte] $addr16 1 none [hl + b] 1st operand [hl + c] a add mov mov mov mov mov mov mov mov ror addc xch xch xch xch xch xch xch rol sub add add add add add rorc subc addc addc addc addc addc rolc and sub sub sub sub sub or subc subc subc subc subc xor and and and and and cmp or or or or or xor xor xor xor xor cmp cmp cmp cmp cmp r mov mov inc add dec addc sub subc and or xor cmp r1 dbnz sfr mov mov saddr mov mov dbnz inc add dec addc sub subc and or xor cmp !addr16 mov psw mov mov push pop [de] mov [hl] mov ror4 rol4 [hl + byte] mov [hl + b] [hl + c] x mulu c divuw note except r = a
m pd78094, 78095, 78096, 78098a 35 (2) 16-bit instructions movw, xchw, addw, subw, cmpw, push, pop, incw, decw 2nd operand #word ax rp note sfrp saddrp !addr16 sp none 1st operand ax addw movw movw movw movw movw subw xchw cmpw rp movw movw note incw, decw push, pop sfrp movw movw saddrp movw movw !addr16 movw sp movw movw note only when rp = bc, de, hl (3) bit manipulation instructions mov1, and1, or1, xor1, set1, clr1, not1, bt, bf, btclr 2nd operand a.bit sfr.bit saddr.bit psw.bit [hl].bit cy $addr16 none 1st operand a.bit mov1 bt set1 bf clr1 btclr sfr.bit mov1 bt set1 bf clr1 btclr saddr.bit mov1 bt set1 bf clr1 btclr psw.bit mov1 bt set1 bf clr1 btclr [hl].bit mov1 bt set1 bf clr1 btclr cy mov1 mov1 mov1 mov1 mov1 set1 and1 and1 and1 and1 and1 clr1 or1 or1 or1 or1 or1 not1 xor1 xor1 xor1 xor1 xor1
m pd78094, 78095, 78096, 78098a 36 (4) call instruction/branch instructions call, callf, callt, br, bc, bnc, bz, bnz, bt, bf, btclr, dbnz 2nd operand ax !addr16 !addr11 [addr5] $addr16 1st operand basic instruction br call callf callt br, bc, br bnc, bz, bnz compound instruction bt, bf btclr dbnz (5) other instructions adjba, adjbs, brk, ret, reti, retb, sel, nop, ei, di, halt, stop
m pd78094, 78095, 78096, 78098a 37 11. electrical specifications absolute maximum ratings (t a = 25 c) parameter symbol test conditions ratings unit supply voltage v dd C0.3 to +7.0 v av dd C0.3 to v dd + 0.3 v av ref0 C0.3 to v dd + 0.3 v av ref1 C0.3 to v dd + 0.3 v av ss C0.3 to +0.3 v input voltage v i1 p00-p07, p10-p17, p20-p27, p30-p37, C0.3 to v dd + 0.3 v p40-p47, p50-p57, p64-p67, p70-p72, p120-p127, p130, p131, x1, x2, xt2, reset v i2 p60-p63 n-ch open-drain C0.3 to +16 v output voltage v o C0.3 to v dd + 0.3 v analog input voltage v an p10-p17 analog input pins av ss C 0.3 to av ref0 + 0.3 v output current, high i oh per pin C10 ma total for p01-p06, p30-p37, p56, p57, C15 ma p60-p67, p120-p127 total for p10-p17, p20-p27, p40-p47, C15 ma p50-p55, p70-p72, p130, p131 output current, low i ol note per pin peak value 30 ma r.m.s. value 15 ma total for p50-p55 peak value 100 ma r.m.s. value 70 ma total for p56, p57, p60-p63 peak value 100 ma r.m.s. value 70 ma total for p10-p17, p20-p27, peak value 50 ma p40-p47, p70-p72, p130, p131 r.m.s. value 20 ma total for p01-p06, p30-p37, peak value 50 ma p64-p67, p120-p127 r.m.s. value 20 ma operating ambient temperature t a C40 to +85 c storage temperature t stg C65 to +150 c power dissipation p d 650 mw note the r.m.s. value should be calculated as follows: [r.m.s. value] = [peak value] x duty caution exposure to absolute maximum ratings for extended periods may affect device reliablity; exceeding the ratings could cause permanent damege. the parameters apply independently. remark unless otherwise specified, dual-function pin characteristics are the same as port pin characteristics.
m pd78094, 78095, 78096, 78098a 38 main system clock oscillator characteristics (t a = C40 to +85 c, v dd = 2.7 to 5.5 v) ic c1 x1 c2 r1 x2 resonator recommended parameter test conditions min. typ. max. unit circuit ceramic oscillation frequency v dd = oscillation voltage 1.0 6.0 6.29 mhz resonator (f x ) note 1 range oscillation stabilization after v dd came to min. 4 ms time note 2 of oscillation voltage range crystal oscillation frequency 1.0 6.0 6.29 mhz resonator (f x ) note 1 oscillation stabilization v dd = 4.5 to 5.5 v 10 ms time note 2 30 external clock x1 input frequency 1.0 6.0 6.29 mhz (f x ) note 1 x1 input high- and using at f xx = f x 85 500 ns low-level widths (t xh , t xl ) other than above 72 500 ic c1 x1 c2 r1 x2 x1 x2 pd74hcu04 m notes 1. only the oscillator characteristics are shown. for instruction execution time, refer to ac characteristics. 2. time required for oscillation to stabilize after a reset or the stop mode has been released. cautions 1. when using the main system clock oscillator, wire the portion enclosed in dotted line in the figures as follows to avoid adverse influences on the wiring capacitance: ? keep the wiring length as short as possible. ? do not cross the wiring over other signal lines. ? do not route the wiring in the vicinity of lines through which a high fluctuating current flows. ? always keep the ground point of the capacitor of the oscillator circuit at the same potential as v dd . ? do not connect the power source pattern through which a high current flows. ? do not extract signals from the oscillation circuit. 2. when switching on the main system clock again after the subsystem clock has been used with the main system clock stopped, be sure to provide enough time for the generation to be stable with the program first.
m pd78094, 78095, 78096, 78098a 39 resonator recommended parameter test conditions min. typ. max. unit circuit crystal oscillation frequency 32 32.768 35 khz resonator (f x ) note 1 oscillation stabilization v dd = 4.5 to 5.5 v 1.2 2 s time note 2 10 external clock xt1 input frequency 32 100 khz (f xt ) note 1 xt1 input high-, low-level 5 15 m s widths (t xth , t xtl ) notes 1. only the oscillator characteristics are shown. for instruction execution time, refer to ac characteristics. 2. time required for oscillation to stabilize after power (v dd ) is turned on. cautions 1. when using the subsystem clock oscillator, wire the portion enclosed in dotted line in the figures as follows to avoid adverse influences on the wiring capacitance: ? keep the wiring length as short as possible. ? do not cross the wiring over other signal lines. ? do not route the wiring in the vicinity of lines through which a high fluctuating current flows. ? always keep the ground point of the capacitor of the oscillator circuit at the same potential as v dd . ? do not connect the power source pattern through which a high current flows. ? do not extract signals from the oscillation circuit. 2. the amplification factor of the subsystem clock oscillator circuit is designed to be low to reduce the current consumption and therefore, the subsystem clock circuit is influenced by noise more easily than the main system clock oscillator. when using the subsystem clock, therefore, exercise utmost care in wiring the circuit. capacitance (t a = 25 c, v dd = v ss = 0 v) parameter symbol test conditions min. typ. max. unit input capacitance c in f = 1 mhz unmeasured pins returned to 0 v. 15 pf i/o capacitance c io f = 1 mhz p01-p06, p10-p17, p20-p27, 15 pf unmeasured p30-p37, p40-p47, p50-p57, pins returned p64-p67, p70-p72, to 0 v. p120-p127, p130, p131 p60-p63 20 pf subsystem clock oscillator characteristics (t a = C40 to +85 c, v dd = 2.7 to 5.5 v) ic c3 xt1 c4 r2 xt2 xt2 xt1 remark unless otherwise specified, dual-function pin characteristics are the same as port pin characteristics.
m pd78094, 78095, 78096, 78098a 40 parameter symbol test conditions min. typ. max. unit input voltage, high v ih1 p10-p17, p21, p23, p30-p32, p35-p37, p40-p47, 0.7v dd v dd v p50-p57, p64-p67, p71, p120-p127, p130, p131 v ih2 p00-p06, p20, p22, p24-p27, p130, p131 0.8v dd v dd v reset v ih3 p60-p63 n-ch open-drain 0.7v dd 15 v v ih4 x1, x2 v dd C 0.5 v dd v v ih5 xt1/p07, xt2 4.5 v dd 5.5 v 0.8v dd v dd v 2.7 v dd 4.5 v 0.9v dd v dd v input voltage, low v il1 p10-p17, p21, p23,p30-p32, p35-p37, p40-p47 0 0.3v dd v p50-p57, p64-p67, p71, p120-p127, p130, p131 v il2 p00-p06, p20, p22, p24-p27, p33, p34, p70, p72 0 0.2v dd v reset v il3 p60-p63 4.5 v v dd 5.5 v 0 0.3v dd v (n-ch open drain) 2.7 v v dd 4.5 v 0 0.2v dd v v il4 x1, x2 0 0.4 v v il5 xt1/p07, xt2 v dd = 4.5 to 5.5 v 0 0.2v dd v 0 0.1v dd v output voltage, high v oh1 v dd = 4.5 to 5.5 v, i oh = C1 ma v dd C 1.0 v i oh = C100 m a v dd C 0.5 v output voltage, low v ol1 p50-p57, p60-p63 v dd = 4.5 to 5.5 v, 0.4 2.0 v i ol = 15 ma p01-p06, p10-p17, v dd = 4.5 to 5.5 v, 0.4 v p20-p27, p30-p37, i ol = 1.6 ma p40-p47, p64-p67, p70-p72, p120-p127, p130, p131 v ol2 sb0, sb1, sck0 v dd = 4.5 to 5.5 v, 0.2v dd v open-drain pulled high (r = 1 k w ) v ol3 i ol = 400 m a 0.5 v dc characteristics (t a = C40 to +85 c, v dd = 2.7 to 5.5 v) remark unless otherwise specified, dual-function pin characteristics are the same as port pin characteristics.
m pd78094, 78095, 78096, 78098a 41 parameter symbol test conditions min. typ. max. unit input leakage current, high i lih1 v in = v dd p00-p06, p10-p17, 3 m a p20-p27, p30-p37, p40-p47, p50-p57, p60-p67, p70-p72, p120-p127, p130, p131, reset i lih2 x1, x2, xt1/p07, xt2 20 m a i lih3 v in = 15 v p60-p63 80 m a input leakage current, low i lil1 v in = 0 v p00-p06, p10-p17, C3 m a p20-p27, p30-p37, p40-p47, p50-p57, p64-p67, p70-p72, p120-p127, p130, p131, reset i lil2 x1, x2, xt1/p07, xt2 C20 m a i lil3 p60-p63 C3 note m a output leakage current, high i loh v out = v dd 3 m a output leakage current, low i lol v out = 0 v C3 m a mask option pull-up resistor r 1 v in = 0 v, p60-p63 20 40 90 k w software pull-up resistor r 2 v in = 0 v, p01-p06, 4.5 v v dd 5.5 v 15 40 90 k w p10-p17, p20-p27, p30-p37, p40-p47, p50-p57, p64-p67, 2.7 v v dd 4.5 v 20 500 k w p70-p72, p120-p127, p130, p131 dc characteristics (t a = C40 to +85 c, v dd = 2.7 to 5.5 v) note when no pull-up resistor is incorporated to p60-63 (to be specified by mask option), the value is C200 m a in either of the following cases. (1) when external device expansion function is used and low-level is input to p60 to p63 pins. (2) during the 1.5 clocks when read out instruction is executed to port 6 (p6) and port mode register 6 (pm6). remark unless otherwise specified, dual-function pin characteristics are the same as port pin characteristics.
m pd78094, 78095, 78096, 78098a 42 parameter symbol test conditions min. typ. max. unit supply current note 1 i dd1 5.0-mhz crystal oscil- v dd = 5.0 v 10% note 6 415ma lation operating mode v dd = 3.0 v 10% note 7 0.6 2.4 ma (f xx = 2.5 mhz) note 2 5.0-mhz crystal oscil- v dd = 5.0 v 10% note 6 6.5 22.5 ma lation operating mode v dd = 3.0 v 10% note 7 0.8 3.1 ma (f xx = 5.0 mhz) note 3 6.29-mhz crystal oscil- v dd = 5.0 v 10% note 6 3.8 14.5 ma lation operating mode (f xx = 2.1 mhz) note 4 6.29-mhz crystal oscil- v dd = 5.0 v 10% note 6 621ma lation operating mode (f xx = 4.19 mhz) note 5 dc characteristics (t a = C40 to +85 c, v dd = 2.7 to 5.5 v) notes 1. not including av ref0 , av ref1 , av dd currents and port currents (including current flowing into on-chip pull-up resistors). 2. when bit 0 of the clock switch selection register 1 is set to 0, bit 0 of the clock switch selection register 2 is set to 0, and oscillation mode selection register is set to 00h. 3. when bit 0 of the clock switch selection register 1 is set to 0, bit 0 of the clock switch selection register 2 is set to 0, and oscillation mode selection register is set to 01h. 4. when bit 0 of the clock switch selection register 1 is set to 1, bit 0 of the clock switch selection register 2 is set to 0, and oscillation mode selection register is set to 00h. only the characteristics of the supply current are shown. for the iebus standards, refer to iebus controller characteristics. 5. when bit 0 of the clock switch selection register 1 is set to 1, bit 0 of the clock switch selection register 2 is set to 0, and oscillation mode selection register is set to 01h. only the characteristics of the supply current are shown. for the iebus standards, refer to iebus controller characteristics. 6. high-speed mode operation (when processor clock control register is set to 00h). 7. low-speed mode operation (when processor clock control register is set to 04h). remark f xx : main system clock frequency.
m pd78094, 78095, 78096, 78098a 43 dc characteristics (t a = C40 to +85 c, v dd = 2.7 to 5.5 v) parameter symbol test conditions min. typ. max. unit supply current note 1 i dd2 5.0-mhz crystal oscil- v dd = 5.0 v 10% note 7 1.5 4.5 ma lation halt mode v dd = 3.0 v 10% note 8 0.5 1.5 ma (f xx = 2.5 mhz) note 2 5.0-mhz crystal oscil- v dd = 5.0 v 10% note 7 1.8 5.4 ma lation halt mode v dd = 3.0 v 10% note 8 0.7 2.1 ma (f xx = 5.0 mhz) note 3 6.29-mhz crystal oscil- v dd = 5.0 v 10% note 7 1.5 4.5 ma lation halt mode (f xx = 2.1 mhz) note 4 6.29-mhz crystal oscil- v dd = 5.0 v 10% note 7 1.8 5.4 ma lation halt mode (f xx = 4.19 mhz) note 5 i dd3 32.768-khz v dd = 5.0 v 10% 60 120 m a crystal oscillation v dd = 3.0 v 10% 32 64 m a operating mode note 6 i dd4 32.768-khz v dd = 5.0 v 10% 25 55 m a crystal oscillation v dd = 3.0 v 10% 5 15 m a halt mode note 6 i dd5 xt1 = 0 v v dd = 5.0 v 10% 1 30 m a stop mode, feed- v dd = 3.0 v 10% 0.5 10 m a back resistor used i dd6 xt1 = 0 v v dd = 5.0 v 10% 0.1 30 m a stop mode, feed- v dd = 3.0 v 10% 0.05 10 m a back resistor not used notes 1. not including av ref0 , av ref1 , av dd currents and port currents (including current flowing into internal pull-up resistors). 2. when bit 0 of the clock switch selection register 1 is set to 0, bit 0 of the clock switch selection register 2 is set to 0, and oscillation mode selection register is set to 00h. 3. when bit 0 of the clock switch selection register 1 is set to 0, bit 0 of the clock switch selection register 2 is set to 0, and oscillation mode selection register is set to 01h. 4. when bit 0 of the clock switch selection register 1 is set to 1, bit 0 of the clock switch selection register 2 is set to 0, and oscillation mode selection register is set to 00h. only the characteristics of the supply current are shown. for the iebus standards, refer to iebus controller characteristics. 5. when bit 0 of the clock switch selection register 1 is set to 1, bit 0 of the clock switch selection register 2 is set to 0, and oscillation mode selection register is set to 01h. only the characteristics of the supply current are shown. for the iebus standards, refer to iebus controller characteristics. 6. when the main system clcok is stopped. 7. high-speed mode operation (when processor clock control register is set to 00h). 8. low-speed mode operation (when processor clock control register is set to 04h). remark f xx : main system clock frequency.
m pd78094, 78095, 78096, 78098a 44 notes 1. when oscillation mode selection register is set to 00h. 2. when oscillation mode selection register is set to 01h. 3. f sam can be selected as f xx /2 n , f xx /32, f xx /64, or f xx /128 (n = 0 to 4) by bits 0 and 1 (scs0, scs1) of the sampling clock selection register. remarks 1. f xx : main system clock frequency (fx or fx/2). 2. f x : main system clock oscillation frequency. ac characteristics (1) basic operation (t a = C40 to +85 c, v dd = 2.7 to 5.5 v) parameter symbol test conditions min. typ. max. unit cycle time t cy operating on f xx = f x /3 4.0 v dd 5.5 v 0.95 64 m s (minimum instruction execution main system clock f xx = f x /6 2.7 v dd 5.5 v 1.91 64 m s time) (mcs = 0) note1 f xx = f x /9 4.0 v dd 5.5 v 2.86 64 m s f xx = f x /2 2.7 v dd 5.5 v 0.8 64 m s operating on f xx = 2f x /3 4.5 v dd 5.5 v 0.48 32 m s main system clock 4.0 v dd 4.5 v 0.95 32 m s (mcs = 1) note2 f xx = f x /3 2.7 v dd 5.5 v 0.95 32 m s f xx = 2f x /9 4.0 v dd 5.5 v 1.43 32 m s f xx = f x 4.5 v dd 5.5 v 0.4 32 m s 2.7 v dd 4.5 v 0.8 32 m s operating on subsystem clock 114 122 125 m s ti input frequency f ti ti1, ti2 v dd = 4.5 to 5.5 v 0 4 mhz 0 275 khz ti01 0 50 khz ti00 0 f sam /16 note3 mhz ti input high-, low-level t tih , ti1, ti2 v dd = 4.5 to 5.5 v 100 ns widths t til 1.8 m s ti01 10 m s ti00 8/f sam note3 m s interrupt input high-, low-level t inth , intp0 8/f sam note3 m s widths t intl intp1-intp6 10 m s kr0-kr7 10 m s reset low-level width t rst 10 m s
m pd78094, 78095, 78096, 78098a 45 60 10 2.0 1.0 0.5 0.4 0 123456 power supply voltage v dd [v] cycle time t cy [ s] m operation guaranteed range 60 10 2.0 1.0 0.5 0.4 0 123456 power supply voltage v dd [v] cycle time t cy [ s] m operation guaranteed range 60 10 2.0 1.0 0.5 0.4 0 123456 power supply voltage v dd [v] cycle time t cy [ s] m operation guaranteed range 60 10 2.0 1.0 0.5 0.4 0 123456 power supply voltage v dd [v] cycle time t cy [ s] m operation guaranteed range t cy vs v dd main system clock t cy vs v dd main system clock (iecl10 = 0, iecl20 = 0, mcs = 0) operation (iecl10 = 1, iecl20 = 0, mcs = 0) operation t cy vs v dd main system clock t cy vs v dd main system clock (iecl10 = 0, iecl20 = 1, mcs = 0) operation (iecl10 = 1, iecl20 = 1, mcs = 0) operation
m pd78094, 78095, 78096, 78098a 46 60 10 2.0 1.0 0.5 0.4 0 123456 power supply voltage v dd [v] cycle time t cy [ s] m operation guaranteed range 60 10 2.0 1.0 0.5 0.4 0 123456 power supply voltage v dd [v] cycle time t cy [ s] m operation guaranteed range 60 10 2.0 1.0 0.5 0.4 0 123456 power supply voltage v dd [v] cycle time t cy [ s] m operation guaranteed range 60 10 2.0 1.0 0.5 0.4 0 123456 power supply voltage v dd [v] cycle time t cy [ s] m operation guaranteed range t cy vs v dd main system clock t cy vs v dd main system clock (iecl10 = 0, iecl20 = 0, mcs = 1) operation (iecl10 = 1, iecl20 = 0, mcs = 1) operation t cy vs v dd main system clock t cy vs v dd main system clock (iecl10 = 0, iecl20 = 1, mcs = 1) operation (iecl10 = 1, iecl20 = 1, mcs = 1) operation
m pd78094, 78095, 78096, 78098a 47 (2) read/write operation (a) when mcs = 1, pcc2-pcc0 = 000b (t a = C40 to +85 c, v dd = 4.5 to 5.5 v) parameter symbol test conditions min. max. unit astb high-level width t asth 0.85t cy C 50 ns address setup time t ads 0.85t cy C 50 ns address hold time t adh 50 ns address ? data input time t add1 (2.85 + 2n) t cy C 80 ns t add2 (4 + 2n) t cy C 100 ns rd ? data input time t rdd1 (2 + 2n) t cy C 100 ns t rdd2 (2.85 + 2n) t cy C 100 ns read data hold time t rdh 0ns rd low-level width t rdl1 (2 + 2n) t cy C 60 ns t rdl2 (2.85 + 2n) t cy C 60 ns rd ? wait input time t rdwt1 0.85t cy C 50 ns t rdwt2 2t cy C 60 ns wr ? wait input time t wrwt 2t cy C 60 ns wait low-level width t wtl (1.15 + 2n) t cy (2 + 2n) t cy ns write data setup time t wds (2.85 + 2n) t cy C 100 ns write data hold time t wdh 20 ns wr low-level width t wrl (2.85 + 2n) t cy C 60 ns astb ? rd delay time t astrd 25 ns astb ? wr delay time t astwr 0.85t cy + 20 ns in external fetch rd - ? t rdast 0.85t cy C 10 1.15t cy + 20 ns astb - delay time in external fetch rd - ? t rdadh 0.85t cy C 50 1.15t cy + 50 ns address hold time rd - ? write data output time t rdwd 40 ns wr ? write data output time t wrwd 050ns wr - ? address hold time t wradh 0.85t cy + 40 1.15t cy + 40 ns wait - ? rd - delay time t wtrd 1.15t cy + 40 3.15t cy + 40 ns wait - ? wr - delay time t wtwr 1.15t cy + 30 3.15t cy + 30 ns remarks 1. mcs: bit 0 of the oscillation mode selection register. 2. pcc2-pcc0: bit 2-bit 0 of the processor clock control register. 3. t cy = t cy /4. 4. n indicates the number of waits.
m pd78094, 78095, 78096, 78098a 48 (b) except when mcs = 1, pcc2-pcc0 = 000b (t a = C40 to +85 c, v dd = 2.7 to 5.5 v) parameter symbol test conditions min. max. unit astb high-level width t asth t cy C 80 ns address setup time t ads t cy C 80 ns address hold time t adh 0.4t cy C 10 ns address ? data input time t add1 (3 + 2n) t cy C 160 ns t add2 (4 + 2n) t cy C 200 ns rd ? data input time t rdd1 (1.4 + 2n) t cy C 70 ns t rdd2 (2.4 + 2n) t cy C 70 ns read data hold time t rdh 0ns rd low-level width t rdl1 (1.4 + 2n) t cy C 20 ns t rdl2 (2.4 + 2n) t cy C 20 ns rd ? wait input time t rdwt1 t cy C 100 ns t rdwt2 2t cy C 100 ns wr ? wait input time t wrwt 2t cy C 100 ns wait low-level width t wtl (1 + 2n) t cy (2 + 2n) t cy ns write data setup time t wds (2.4 + 2n) t cy C 60 ns write data hold time t wdh 20 ns wr low-level width t wrl (2.4 + 2n) t cy C 20 ns astb ? rd delay time t astrd 0.4t cy C 30 ns astb ? wr delay time t astwr 1.4t cy C30 ns in external fetch rd - ? t rdast t cy C 10 t cy + 20 ns astb - delay time in external fetch rd - ? t rdadh t cy C 50 t cy + 50 ns address hold time rd - ? write data output time t rdwd 0.4t cy C 20 ns wr ? write data output time t wrwd 060ns wr - ? address hold time t wradh t cy t cy + 60 ns wait - ? rd - delay time t wtrd 0.6t cy + 180 2.6t cy + 180 ns wait - ? wr - delay time t wtwr 0.6t cy + 120 2.6t cy + 120 ns remarks 1. mcs: bit 0 of the oscillation mode selection register. 2. pcc2-pcc0: bit 2-bit 0 of the processor clock control register. 3. t cy = t cy /4. 4. n indicates the number of waits.
m pd78094, 78095, 78096, 78098a 49 (3) serial interface (t a = C40 to +85 c, v dd = 2.7 to 5.5 v) (a) serial interface channel 0 (i) 3-wire serial i/o mode (sck0 internal clock output) parameter symbol test conditions min. typ. max. unit sck0 cycle time t kcy1 v dd = 4.5 to 5.5 v 800 ns 1600 ns sck0 high-/low-level widths t kh1 ,v dd = 4.5 to 5.5 v t kcy1 /2C50 ns t kl1 t kcy1 /2C100 ns si0 setup time t sik1 v dd = 4.5 to 5.5 v 100 ns (to sck0 - ) 150 ns si0 hold time (from sck0 - )t ksi1 400 ns sck0 ? so0 t kso1 c = 100 pf note 300 ns output delay time note c is the so0 output line load capacitance. (ii) 3-wire serial i/o mode (sck0 external clock input) parameter symbol test conditions min. typ. max. unit sck0 cycle time t kcy2 v dd = 4.5 to 5.5 v 800 ns 1600 ns sck0 high-/low-level widths t kh2 ,v dd = 4.5 to 5.5 v 400 ns t kl2 800 ns si0 setup time t sik2 100 ns (to sck0 - ) si0 hold time (from sck0 - )t ksi2 400 ns sck0 ? so0 t kso2 c = 100 pf note 300 ns output delay time sck0 rise, fall time t r2 , when using external device expansion 160 ns t f2 function when not using external device 1000 ns expansion function note c is the so0 output line load capacitance.
m pd78094, 78095, 78096, 78098a 50 (iii) sbi mode (sck0 internal clock output) parameter symbol test conditions min. typ. max. unit sck0 cycle time t kcy3 v dd = 4.5 to 5.5 v 800 ns 3200 ns sck0 high-/low-level widths t kh3 ,v dd = 4.5 to 5.5 v t kcy3 /2C50 ns t kl3 t kcy3 /2C150 ns sb0, sb1 setup time t sik3 v dd = 4.5 to 5.5 v 100 ns (to sck0 - ) 300 ns sb0, sb1 hold time t ksi3 t kcy3 /2 ns (from sck0 - ) sck0 ? sb0, sb1 t kso3 r = 1 k w ,v dd = 4.5 to 5.5 v 0 250 ns output delay time c = 100 pf note 0 1000 ns sck0 - ? sb0, sb1 t ksb t kcy3 ns sb0, sb1 ? sck0 t sbk t kcy3 ns sb0, sb1 high-level width t sbh t kcy3 ns sb0, sb1 low-level width t sbl t kcy3 ns note r and c are the sb0 and sb1 output line load resistance and load capacitance. (iv) sbi mode (sck0 external clock input) parameter symbol test conditions min. typ. max. unit sck0 cycle time t kcy4 v dd = 4.5 to 5.5 v 800 ns 3200 ns sck0 high-/low-level widths t kh4 ,v dd = 4.5 to 5.5 v 400 ns t kl4 1600 ns sb0, sb1 setup time t sik4 v dd = 4.5 to 5.5 v 100 ns (to sck0 - ) 300 ns sb0, sb1 hold time t ksi4 t kcy4 /2 ns (from sck0 - ) sck0 ? sb0, sb1 t kso4 r = 1 k w ,v dd = 4.5 to 5.5 v 0 300 ns output delay time c = 100 pf note 0 1000 ns sck0 - ? sb0, sb1 t ksb t kcy4 ns sb0, sb1 ? sck0 t sbk t kcy4 ns sb0, sb1 high-level width t sbh t kcy4 ns sb0, sb1 low-level width t sbl t kcy4 ns sck0 rise, fall time t r4 , when using external device expansion 160 ns t f4 function when not using external device 1000 ns expansion function note r and c are the sb0 and sb1 output line load resistance and load capacitance.
m pd78094, 78095, 78096, 78098a 51 (v) 2-wire serial i/o mode (sck0 internal clock input) parameter symbol test conditions min. typ. max. unit sck0 cycle time t kcy5 r = 1 k w ,v dd = 4.5 to 5.5 v 1600 ns c = 100 pf note 3200 ns sck0 high-level widths t kh5 t kcy5 /2C160 ns sck0 low-level width t kl5 v dd = 4.5 to 5.5 v t kcy5 /2C50 ns sb0, sb1 setup time t sik5 v dd = 4.5 to 5.5 v 100 ns (to sck0 - ) 150 ns sb0, sb1 hold time t ksi5 600 ns (from sck0 - ) sck0 ? sb0, sb1 t kso5 0 300 ns output delay time note r and c are the sck0, sb0, and sb1 output line load resistance and load capacitance. (vi) 2-wire serial i/o mode (sck0 external clock input) parameter symbol test conditions min. typ. max. unit sck0 cycle time t kcy6 v dd = 4.5 to 5.5 v 1600 ns 3200 ns sck0 high-level widths t kh6 650 ns sck0 low-level width t kl6 800 ns sb0, sb1 setup time t sik6 100 ns (to sck0 - ) sb0, sb1 hold time t ksi6 t kcy6 /2 ns (from sck0 - ) sck0 ? sb0, sb1 t kso6 r = 1 k w , c = 100 pf note 0 300 ns output delay time sck0 rise, fall time t r6 , when using external device expansion 160 ns t f6 function when not using external device 1000 ns expansion function note r and c are the sck0, sb0, and sb1 output line load resistance and load capacitance.
m pd78094, 78095, 78096, 78098a 52 (b) serial interface channel 1 (i) 3-wire serial i/o mode (sck1 internal clock output) parameter symbol test conditions min. typ. max. unit sck1 cycle time t kcy7 v dd = 4.5 to 5.5 v 800 ns 1600 ns sck1 high-/low-level widths t kh7 ,v dd = 4.5 to 5.5 v t kcy7 /2C50 ns t kl7 t kcy7 /2C100 ns si1 setup time t sik7 v dd = 4.5 to 5.5 v 300 ns (to sck1 - ) 350 ns si1 hold time t ksi7 400 ns (from sck1 - ) sck1 ? so1 t kso7 c = 100 pf note 300 ns output delay time note c is the so1 output line load capacitance. (ii) 3-wire serial i/o mode (sck1 external clock input) parameter symbol test conditions min. typ. max. unit sck1 cycle time t kcy8 v dd = 4.5 to 5.5 v 800 ns 1600 ns sck1 high-/low-level widths t kh8 ,v dd = 4.5 to 5.5 v 400 ns t kl8 800 ns si1 setup time t sik8 100 ns (to sck1 - ) si1 hold time t ksi8 400 ns (from sck1 - ) sck1 ? so1 t kso8 c = 100 pf note 300 ns output delay time sck1 rise, fall time t r8 , when using external device expansion 160 ns t f8 function when not using external device 1000 ns expansion function note c is the so1 output line load capacitance.
m pd78094, 78095, 78096, 78098a 53 (iii) automatic transmission/reception function 3-wire serial i/o mode (sck1 internal clock output) parameter symbol test conditions min. typ. max. unit sck1 cycle time t kcy9 v dd = 4.5 to 5.5 v 800 ns 1600 ns sck1 high-/low-level widths t kh9 ,v dd = 4.5 to 5.5 v t kcy9 /2C50 ns t kl9 t kcy9 /2C100 ns si1 setup time (to sck1 - )t sik9 v dd = 4.5 to 5.5 v 100 ns 150 ns si1 hold time (from sck1 - )t ksi9 400 ns sck1 ? so1 t kso9 c = 100 pf note v dd = 4.5 to 5.5 v 300 ns output delay time sck1 - ? stb - t sbd t kcy9 /2C100 t kcy9 /2+100 ns strobe signal high-level width t sbw t kcy3 C30 t kcy3 +30 ns busy signal setup time t bys 100 ns (to busy signal detection timing) busy signal hold time t byh v dd = 4.5 to 5.5 v 100 ns (from busy signal detection timing) 150 ns busy inactivation ? sck1 t sps 2t kcy9 ns note c is the so1 output line load capacitance. (iv) automatic transmission/reception function 3-wire serial i/o mode (sck1 external clock input) parameter symbol test conditions min. typ. max. unit sck1 cycle time t kcy10 v dd = 4.5 v to 5.5 v 800 ns 1600 ns sck1 high-/low-level widths t kh10 ,v dd = 4.5 v to 5.5 v 400 ns t kl10 800 ns si1 setup time (to sck1 - )t sik10 100 ns si1 hold time (from sck1 - )t ksi10 400 ns sck1 ? so1 t kso10 c = 100 pf note 300 ns output delay time sck1 rise, fall time t r10 , when using external device expansion 160 ns t f10 function when not using external device 1000 ns expansion function note c is the so1 output line load capacitance.
m pd78094, 78095, 78096, 78098a 54 (c) serial interface channel 2 (i) 3-wire serial i/o mode (sck2 internal clock output) parameter symbol test conditions min. typ. max. unit sck2 cycle time t kcy11 v dd = 4.5 to 5.5 v 800 ns 1600 ns sck2 high-/low-level widths t kh11 ,v dd = 4.5 to 5.5 v t kcy11 /2C50 ns t kl11 t kcy11 /2C100 ns si2 setup time t sik11 v dd = 4.5 to 5.5 v 100 ns (to sck2 - ) 150 ns si2 hold time t ksi11 400 ns (from sck2 - ) sck2 ? so2 t kso11 c = 100 pf note 300 ns output delay time note c is the so2 output line load capacitance. (ii) 3-wire serial i/o mode (sck2 external clock input) parameter symbol test conditions min. typ. max. unit sck2 cycle time t kcy12 v dd = 4.5 to 5.5 v 800 ns 1600 ns sck2 high-/low-level widths t kh12 ,v dd = 4.5 to 5.5 v 400 ns t kl12 800 ns si2 setup time t sik12 100 ns (to sck2 - ) si2 hold time t ksi12 400 ns (from sck2 - ) sck2 ? so2 t kso12 c = 100 pf note 300 ns output delay time sck2 rise, fall time t r12 , when using external device expansion 160 ns t f12 function when not using external device 1000 ns expansion function note c is the so2 output line load capacitance.
m pd78094, 78095, 78096, 78098a 55 (iii) uart mode (dedicated baud rate generator output) parameter symbol test conditions min. typ. max. unit transfer rate v dd = 4.5 to 5.5 v 78125 bps 39063 bps (iv) uart mode (external clock input) parameter symbol test conditions min. typ. max. unit asck cycle time t kcy13 v dd = 4.5 to 5.5 v 800 ns 1600 ns asck high-/low-level widths t kh13 ,v dd = 4.5 to 5.5 v 400 ns t kl13 800 ns transfer rate v dd = 4.5 to 5.5 v 39063 bps 19531 bps asck rise, fall time t r13 , when using external device expansion 160 ns t f13 function when not using external device 1000 ns expansion function
m pd78094, 78095, 78096, 78098a 56 1/f ti t til t tih ti00, ti01, t11, t12 1/f xt t xtl t xth v dd ?0.5 v 0.4 v xt1 input 1/f x t xl t xh v dd ?0.5 v 0.4 v x1 input 0.8v dd 0.2v dd 0.8v dd 0.2v dd test points ac timing test point (excluding x1, xt1 input) clock timing ti timing
m pd78094, 78095, 78096, 78098a 57 a8-a15 ad0-ad7 astb rd t ads t asth t adh t rdd1 hi-z t add1 t astrd t rdl1 t rdh t rdadh t rdast instruction code low-order 8-bit address high-order 8-bit address read/write operations external fetch (no wait): external fetch (wait insertion): a8-a15 ad0-ad7 astb rd wait t ads t rdd1 hi-z t add1 t astrd t rdl1 t rdast t wtl t wtrd t rdh t rdadh t adh t asth t rdwt1 instruction code low-order 8-bit address high-order 8-bit address
m pd78094, 78095, 78096, 78098a 58 a8-a15 ad0-ad7 astb rd wr wait hi-z hi-z hi-z t wds t add2 t rdl2 t wrl t astwr t ads t asth t adh read data write data t rdh t wrwd t rdwd t rdd2 t wradh t astrd t wdh t wtl t wtrd t wtl t rdwt2 t wrwt t wtwr low-order 8-bit address high-order 8-bit address a8-a15 ad0-ad7 astb rd wr hi-z hi-z hi-z t wds t add2 t astrd t rdl2 t wrl t wradh t astwr t rdd2 t ads t asth t adh low-order 8-bit address read data write data t rdh t wdh t wrwd t rdwd high-order 8-bit address external data access (no wait): external data access (wait insertion):
m pd78094, 78095, 78096, 78098a 59 sck0 t kl3,4 t r4 t f4 t kcy3,4 t sik3,4 t ksi3,4 t kso3,4 sb0, sb1 t kh3,4 t sbk t ksb sck0 t kl3,4 t kcy3,4 t sik3,4 t ksi3,4 t kso3,4 sb0, sb1 t kh3,4 t sbk t sbh t sbl t ksb t f4 t r4 serial transfer timing 3-wire serial i/o mode: sbi mode (bus release signal transfer): sbi mode (command signal transfer): t ksom sck0-sck2 si0-si2 so0-so2 remark m = 1, 2, 7, 8, 11 or 12 n = 2, 8 or 12 input data output data t kcym t khm t klm t sikm t ksim t rn t fn
m pd78094, 78095, 78096, 78098a 60 t byh t sps t bys sck1 busy (active high) 789 note 10 note 10+n note 1 t sik9, 10 t kso9, 10 t kh9, 10 t f10 t r10 t kl9, 10 t kcy9, 10 t sbd t sbw so1 si1 sck1 stb d2 d1 d0 d7 d7 d0 d1 d2 t ksi9, 10 sck0 t kl5, 6 t kh5, 6 t kcy5, 6 t sik5, 6 t ksi5, 6 sb0,1 t kso5, 6 t r6 t f6 2-wire serial i/o mode: automatic transmission/reception function 3-wire serial i/o mode: automatic transmission/reception function 3-wire serial i/o mode (busy processing): note the signals are not actually low here, but are represented in this way to show the timing convention.
m pd78094, 78095, 78096, 78098a 61 asck t kl13 t kh13 t r13 t f13 t kcy13 uart mode (external clock input) parameter symbol test conditions min. typ. max. unit resolution 888bit total error note iead = 00h 0.6 % iead = 01h v dd = 4.5 to 5.5 v 1 2.2 % 1.4 2.6 % conversion time t conv 19.1 200 m s sampling time t samp 24/f xx m s analog input voltage v ian av ss av ref0 v reference voltage av ref0 2.7 av dd v av ref0 -av ss resistance r airef0 414 k w a/d converter characteristics (t a = C40 to +85 c, av dd = v dd = 2.7 to 5.5 v, av ss = v ss = 0 v) notes 1. r and c are the d/a converter output pin load resistance and load capacitance. 2. value for one d/a converter channel. note excluding quantization error ( 1/2 lsb). shown as a percentage of the full scale value. remarks 1. f xx : main system clock frequency (f x or f x /2). 2. f x : main system clock oscillation frequency. d/a converter characteristics (t a = C40 to +85 c, v dd = 2.7 to 5.5 v, av ss = v ss = 0 v) parameter symbol test conditions min. typ. max. unit resolution 8 bit total error r = 2 m w note1 1.2 % r = 4 m w note1 0.8 % r = 10 m w note1 0.6 % settling time c = 30 pf note1 v dd = 4.5 to 5.5 v 10 m s 15 m s output resistor r o dacs0, dacs1 = 55h note2 10 k w analog reference voltage av ref1 2.7 v dd v av ref1 current i ref1 note2 1.5 ma
m pd78094, 78095, 78096, 78098a 62 stop instruction execution v dd v dddr standby release signal (interrupt request) operating mode halt mode stop mode data retention mode t wait t srel stop instruction execution v dd v dddr operating mode halt mode stop mode data retention mode t wait reset t srel internal reset operation data memory stop mode low supply voltage data retention characteristics (t a = C40 to 85 c) parameter symbol test conditions min. typ. max. unit data retention supply voltage v dddr 2.0 5.5 v data retention supply current i dddr v dddr = 2.0 v 0.1 10 m a subsystem clock stopped, feedback resistor disconnected release signal setup time t srel 0 m s oscillation stabilization t wait release by reset 2 17 /f x ms wait time release by interrupt note ms note 2 12 /f xx , or 2 14 /f xx through 2 17 /f xx can be selected by bits 0 to 2 (osts0-osts2) of the oscillation stabilization time selection register. remarks f xx : main system clock frequency f x : main system clock oscillation frequency data retention timing (stop mode released by reset) data retention timing (standby released signal: stop mode released by interrupt signal)
m pd78094, 78095, 78096, 78098a 63 interrupt input timing reset input timing reset t rsl iebus controller characteristics (t a = C40 to 85 c, v dd = 5 v 10 %) parameter symbol test conditions min. typ. max. unit iebus controller system clock f s when using mode 0 or mode 1 note1 5.91 6.00 6.09 mhz frequency 6.20 6.29 6.39 mhz when using mode 2 note1 5.97 6.00 6.03 mhz 6.26 6.29 6.32 mhz driver delay time c = 50 pf note2 f s = 6.00 mhz 1.6 m s (tx output ? bus line) f s = 6.29 mhz 1.5 m s receiver delay time f s = 6.00 mhz 0.75 m s (bus line ? rx input) f s = 6.29 mhz 0.7 m s propagation delay time on f s = 6.00 mhz 0.90 m s the bus f s = 6.29 mhz 0.85 m s notes 1. values in lower line do not satisfy the standard as iebus. 2. c is the tx output line load capacitance. intp0-intp6 t intl t inth
m pd78094, 78095, 78096, 78098a 64 (t a = 25 ?) supply current i dd [ma] 10 5.0 1.0 0.5 0.1 0.05 0.01 0.005 0.001 012345678 supply voltage v dd [v] i dd vs v dd (f x = 6.0 mhz, f xx = 2.0 mhz) pcc = 00h pcc = 01h pcc = 02h pcc = 03h pcc = 04h pcc = 30h halt (x1 oscillation, xt1 oscillation) pcc = b0h stop (x1 stop, xt1 oscillation) halt (x1 stop, xt1 oscillation) f xx = 2.0 mhz f xt = 32.768 khz 12. characteristic curves (reference values)
m pd78094, 78095, 78096, 78098a 65 (t a = 25 ?) supply current i dd [ma] 10 5.0 1.0 0.5 0.1 0.05 0.01 0.005 0.001 012345678 supply voltage v dd [v] pcc = 00h pcc = 01h pcc = 02h pcc = 03h pcc = 04h pcc = 30h halt (x1 oscillation, xt1 oscillation) pcc = b0h stop (x1 stop, xt1 oscillation) halt (x1 stop, xt1 oscillation) f xx = 4.0 mhz f xt = 32.768 khz i dd vs v dd (f x = 6.0 mhz, f xx = 4.0 mhz)
m pd78094, 78095, 78096, 78098a 66 13. package drawing a m f b 60 61 40 k l 80 pin plastic qfp ( 14) 80 1 21 20 41 g d c detail of lead end s q p m i h j 55 n s80gc-65-3b9-3 item millimeters inches a b c d f g h i j k l 17.2 0.4 14.0 0.2 0.8 0.30 0.10 0.13 14.0 0.2 0.677 0.016 0.031 0.031 0.005 0.026 (t.p.) 0.551 note m n 0.10 0.15 1.6 0.2 0.65 (t.p.) 0.004 0.006 +0.004 ?.003 each lead centerline is located within 0.13 mm (0.005 inch) of its true position (t.p.) at maximum material condition. 0.063 0.008 0.012 0.551 0.8 0.2 0.031 p 2.7 0.106 0.677 0.016 17.2 0.4 0.8 +0.009 ?.008 q 0.1 0.1 0.004 0.004 s 3.0 max. 0.119 max. +0.10 ?.05 +0.009 ?.008 +0.004 ?.005 +0.009 ?.008
m pd78094, 78095, 78096, 78098a 67 14. recommended soldering conditions these products should be soldered and mounted under the conditions recommended below. for details on the recommended soldering conditions, refer to information document semiconductor device mounting technology manual (iei-1207) . for soldering methods and conditions other than those recommended, please contact your nec sales representative. table 14-1. soldering conditions for surface mount devices m pd78094gc- -3b9: 80-pin plastic qfp (14 x 14 mm) m pd78095gc- -3b9: 80-pin plastic qfp (14 x 14 mm) m pd78096gc- -3b9: 80-pin plastic qfp (14 x 14 mm) m pd78098agc- -3b9: 80-pin plastic qfp (14 x 14 mm) soldering method soldering conditions symbol infrared ray reflow package peak temperature: 235 c, ir35-00-2 reflow time: 30 seconds or less (at 210 c or higher), number of reflow processes: 2 or less < cautions > (1) wait for the device temperature to return to normal after the first reflow before starting the second reflow. (2) do not perform flux cleaning with water after the first reflow. vps package peak temperature: 215 c, vp15-00-2 reflow time: 40 seconds or less (at 200 c or higher), number of reflow processes: 2 or less < cautions > (1) wait for the device temperature to return to normal after the first reflow before starting the second reflow. (2) do not perform flux cleaning with water after the first reflow. wave soldering solder temperature: 260 c or below, ws60-00-1 flow time: 10 seconds or less, number of flow processes: 1, preheating temperature: 120 c max. (package surface temperature) partial heating pin temperature: 300 c or below, flow time: 3 seconds or less (per device side)
m pd78094, 78095, 78096, 78098a 68 appendix a. development tools the following tools are available for system development using the m pd78098 subseries. language processing software ra78k/0 note 1, 2, 3 assembler package used in common for the 78k/0 series cc78k/0 note 1, 2, 3 c compiler package used in common for the 78k/0 series df78098 note 1, 2, 3 device file used for the m pd78098 subseries cc78k/0-l note 1, 2, 3 c compiler library source file used in common for the 78k/0 series prom writing tools pg-1500 prom programmer pa-78p054gc programmer adapter connected to the pg-1500 pa-78p054kk-t pg-1500 controller note 1, 2 control program for the pg-1500 debugging tools ie-78000-r in-circuit emulator used in common for the 78k/0 series ie-78000-r-bk break board used in common for the 78k/0 series ie-78098-r-em emulation board for evaluation of the m pd78098 subseries ep-78230gc-r emulation probe used in common for the m pd78234 subseries ev-9200gc-80 socket mounted on the user system board prepared for 80-pin plastic qfp ev-9900 tool used for removing the m pd78p098akk-t from the ev-9200gf-80. sm78k0 note 4, 5 system simulator used in common for the 78k/0 series sd78k/0 note 1, 2 screen debugger for the ie-78000-r df78098 note 1, 2, 4, 5 device file used for the m pd78098 subseries real-time os rx78k/0 note 1, 2, 3 real-time os used for the 78k/0 series mx78k0 note 1, 2, 3 os used for the 78k/0 series fuzzy inference development support system fe9000 note 1 /fe9200 note 5 fuzzy knowledge data creation tool ft9080 note 1 /ft9085 note 2 translator fi78k0 note 1, 2 fuzzy inference module fd78k0 note 1, 2 fuzzy inference debugger notes 1. based on pc-9800 series (ms-dos tm ) 2. based on ibm pc/at tm (pc dos tm ) 3. based on hp9000 series 300 tm , hp9000 series 700 tm (hp-ux tm ), sparcstation tm (sunos tm ), and ews- 4800 series (ews-ux/v) 4. based on pc-9800 series (ms-dos + windows tm ) 5. based on ibm pc/at (pc dos + windows) remark use the ra78k/0, cc78k/0, sm78k0, and sd78k/0 in combination with the df78098.
m pd78094, 78095, 78096, 78098a 69 appendix b. related documents documents related to devices document document no. japanese english m pd78p098a preliminary product information ip-9135 in preparation m pd78098 subseries users manual ieu-854 ieu-1381 78k/0 series users manualinstructions ieu-849 ieu-1372 78k/0 series instruction table iem-5522 78k/0 series instruction set iem-5521 m pd78098 subseries special function register table iem-5591 78k/0 series application notebasic iii iea-767 in preparation documents related to development tools (user's manual) document document no. japanese english ra78k series assembler package operation eeu-809 eeu-1399 language eeu-815 eeu-1404 ra78k series structured assembler preprocessor eeu-817 eeu-1402 cc78k series c compiler operation eeu-656 eeu-1280 language eeu-655 eeu-1284 cc78k series library source file eeu-777 cc78k/0 c compiler application note programming know-how eea-618 in preparation pg-1500 prom programmer eeu-651 eeu-1335 pg-1500 controller pc-9800 series (ms-dos based) eeu-704 planned pg-1500 controller ibm pc series (pc dos based) eeu-5008 eeu-1291 ie-78000-r eeu-810 eeu-1398 ie-78000-r-bk eeu-867 eeu-1427 ie-78098-r-em eeu-933 eeu-1473 ep-78230 eeu-985 eeu-1515 sm78k0 system simulator reference eeu-5002 in preparation sd78k/0 screen debugger introduction eeu-852 pc-9800 series (ms-dos based) reference eeu-816 sd78k/0 screen debugger introduction eeu-5024 eeu-1414 ibm pc/at (pc dos based) reference eeu-993 eeu-1413 caution the contents of the documents listed above are subject to change without prior notice. make sure to use the latest edition when starting design.
m pd78094, 78095, 78096, 78098a 70 documents related to embedded software (users manual) document document no. japanese english 78k/0 series real-time os basic eeu-912 installation eeu-911 technical eeu-913 78k/0 series os mx78k0 basic eeu-5010 fuzzy knowledge data creation tool eeu-829 eeu-1438 78k/0, 78k/ii, and 87ad series fuzzy inference development support system translator eeu-862 eeu-1444 78k/0 series fuzzy inference development support system fuzzy inference module eeu-858 eeu-1441 78k/0 series fuzzy inference development support system fuzzy inference debugger eeu-921 eeu-1458 other documents document document no. japanese english package manual iei-635 iei-1213 semiconductor device mounting technology manual iei-616 iei-1207 nec semiconductor device quality grades iei-620 iei-1209 nec semiconductor device reliability/quality control system iem-5068 electrostatic discharge (esd) test mem-539 semiconductor device quality assurance guide mei-603 mei-1202 microcomputer-related product guide C third party products C mei-604 caution the contents of the documents listed above are subject to change without prior notice. be sure to use the latest edition when starting design.
m pd78094, 78095, 78096, 78098a 71 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and trans- ported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. fip, iebus, and inter equipment bus are trademarks of nec corporation. ms-dos and windows are trademarks of microsoft corporation. pc/at and pc dos are trademarks of ibm corporation. hp9000 series 300, hp9000 series 700, and hp-ux are trademarks of hewlett packard company. sparcstation is a trademark of sparc international, inc. sunos is a trademark of sun microsystems, inc.
m pd78094, 78095, 78096, 78098a no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customer must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: standard, special, and specific. the specific quality grade applies only to devices developed based on a customer designated quality assurance program for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard:computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices in standard unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 94.11 the export of this product from japan is regulated by the japanese government. to export this product may be prohibited without governmental license, the need for which must be judged by the customer. the export or re-export of this product from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such.

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